1. Field of the Invention
The present invention is related, in general, to flash memories, in particular, to an improvement of write access time of flash memories.
2. Description of the Related Art
One of the issues of flash memories is long write access time. The long write access time of flash memories often restricts the use of the flash memories.
In order to reduce write access time, build-in page buffer architecture has been developed. A typical build-in page buffer flash memory includes a static random access memory (SRAM), which has a fast read/write access time, as a page buffer. Write data is temporarily stored in the SRAM-based page buffer, and then transferred from the page buffer to the flash memory array.
FIG. 1 is a block diagram of a typical build-in page buffer flash memory. The conventional flash memory is composed of an address buffer 1, an I/O buffer 2, a page buffer 4, a comparator circuit 85, a sense amplifier 6, a write amplifier 7, a memory cell array 8, a row decoder 9, a column decoder 10, an internal address generator 11, and a sequence control circuit 92.
The address buffer 1 receives an address signal indicative of a write address from an external system, and generates a page address and a column address in response to the address signal. The page address consists of a part of the write address, and the column address is another part of the received write address.
The I/O buffer 2 provides an interface to achieve exchange of data between the page buffer 4 and the external system. The I/O buffer 2 receives write data from the external system, and outputs read data received from the memory cell array 8.
The memory cell array 8 includes flash memory cells arranged in rows and columns. The memory area of the memory cell array 8 is divided into a plurality of blocks addressable by the write address. Erasing data within the memory cell array 8 is executed in units of blocks.
The page buffer 4 is used to temporarily store the write data received through the I/O buffer 2. The size of the page buffer 4 is the same as the block size, which is typically 1024 bits. The memory area of the page buffer 4 is divided into 32 pages, each of which consists of 32 bits. The pages of the page buffer 4 are addressable by the page address received from the address buffer 1.
The sense amplifier 6 obtains 32-bit data from the addressed block of the memory cell array 8, and outputs the obtained 32-bit data to the comparator circuit 85.
The comparator circuit 85 receives 32-bit data from the page buffer 4, and compares the data received from the page buffer 4 with the data received from the memory cell array 8 to generate a write enable signal 21 and a write error detection signal 20. The write enable signal 21 is representative of whether the requested data write requires programming flash memory cells, and the write error detection signal 20 is representative of whether the requested data write is invalid.
The comparator circuit 85 is used for pre-verification and post-verification of data within the page buffer 4. The pre-verification of the data within the page buffer 4 designates the data verification executed before data write for determining the necessity and validity of the data write of the data within the page buffer 4 into the memory cell array 8. The pre-verification involves comparing the data stored in the page buffer 4 with the data stored in the addressed block, which is selected by the write address as the destination of the data write. The post-verification designates data verification of the write data after the write operation for ensuring that the data write is successfully completed.
The comparator circuit 85 includes 32 comparators, each of which receives one of the data bits from the page buffer 4 and the associated one of the data bits from the sense amplifier 6. FIG. 2 shows a truth table describing operations of the comparators within the comparator circuit 85. Each signal bit of the write enable signal 21 is activated (or set to logic “1”) when the associated one of the data bits from page buffer 4 is logic “0”, and the associated one from the sense amplifier 6 is logic “1”; otherwise the signal bit of the write enable signal 21 is deactivated (or set to logic “0”). On the other hand, each signal bit of the write error detection signal 20 is activated when the associated one of the data bits from page buffer 104 is logic “0”, and the associated one from the sense amplifier 106 is logic “1”; otherwise the signal bit of the write error detection signal 20 is deactivated.
The write amplifier 7 writes the 32-bit data received from the page buffer 4 into the memory cell array 8 through the row decoder 9.
The row decoder 9 selects a row of the memory cells to be accessed in response to an internal address generated by the internal address generator 11.
The column decoder 10 selects a column of the memory cells to be accessed in response to the column address received from the address buffer 1.
The internal address generator 11 generates and provides the internal address for the row decoder 9 and the page buffer 4 under the control of the sequence control circuit 92. The internal address generator 11 increments the internal address by one in response to a control signal received from the sequence control circuit 92.
The sequence control circuit 92 controls the write operation in response to the write error detection signal 20 and the write enable signal 21. The sequence control circuit 92 quits the write operation when any signal bit of the write error detection signal 20 is activated during pre-verification. In addition, the sequence control circuit 92 monitors the write enable signal 21, and disables the data write of the data within the selected page of the page buffer 4 when the data within the selected page is identical to the data within the addressed location in the memory cell array 8, which is selected as the destination of the data write.
As described, a write operation of flash memories requires pre-verification of the write data. One of the reasons is the unidirectional data write operation of the flash memories as described below. The architecture of the flash memory allows programming memory cells independently (that is, allows setting respective memory cells to logic “0” independently); however, the architecture requires erasing memory cells in units of blocks. Therefore, writing logic “1” into a memory cell requires erasure of the whole block including the memory cell. It should be noted that an erased memory cell represents logic “1” while a programmed memory cell represents logic “0”. In other word, data write involving writing logic “1” in a single memory cell is not allowable. Therefore, the validity of a requested data write must be determined before the requested data write is executed.
Another reason is the limited erase/rewrite life of flash memory cells. An unnecessary rewrite operation is preferably avoided for improving the erase/rewrite life of flash memory cells. Therefore, when the data to be written in a memory cell is identical to the data already stored in the memory cell, the data write to the memory cell should be quit.
FIG. 3 shows a typical procedure of a write operation of flash memories. The procedure begins with an input of a page write command. In response to the page write command, the page buffer 4 is initialized to set all the data bits of the page buffer 4 to logic “1” at Step 101. At Step 102, a write address and write data are then received by the address buffer 1 and I/O buffer 2, respectively. The page buffer 4 is addressed by the page address, and the write data is written into the addressed location of the page buffer 4. The memory cell array 8 are also addressed by the write address, and one of the blocks of the memory cell array 8 is selected as the addressed location of the data write.
Pre-verification is then executed by the comparator 85 at Step 103 to determine the necessity and validity of the data write by comparing the data within the page buffer 4 with the data within the addressed block.
In response to the result of the pre-verification, programming of the memory cell array 8 is then executed at Step 104 to write the write data, which is temporary stored in the page buffer 4, into the memory cell array 8. When the write data is identical to the data within the addressed location of the memory cell array 8, the data write is cancelled. When the write data includes one or more bits which require flip of data from logic “0” to logic “1” within the addressed block of the memory cell array 8, the write data is programmed into the addressed block after the addressed block is erased; otherwise, the write data is programmed without erasing the addressed block.
Finally, post-verification is executed at Step 105 to confirm that the write data is correctly written into the addressed block of the memory cell array 8 by comparing the data stored in the addressed block with the data stored in the page buffer 4.
Various built-in page buffer flash memories are disclosed in various document; Japanese Open Laid Patent Application No. 2000-285686 discloses a built-in page buffer flash memory for avoiding incorrect data write. This flash memory includes a flag circuit which stores therein flags, each of which is associated with a byte of data stored in the page buffer. The activation of the each flag represents that the associated byte in the page buffer is rewritten or updated during write operation. After all the flag are activated, the write data is transferred from the page buffer to the memory cell array. This ensures that the page buffer correctly receives the write data, and thus effectively avoids incorrect data write.
Japanese Open Laid Patent Application No. Heisei 6-20487 discloses a built-in page buffer flash memory for avoiding incorrect data write and reducing a number of data rewrite. In this flash memory, the memory cell array includes blocks, each of which consists of a plurality of pages arranged in a row extending in a direction from the sources to drains of the flash memory cells. The page buffer includes a plurality of addressable pages associated with the pages within the each block. The data write is sequentially executed from the page positioned at the source side end to the page positioned at the drain side end, regardless of the order of the data write into the pages of the page buffer. The data write from the page positioned at the source side end effectively avoids incorrect data write, and thus reduces a number of data rewrite after the incorrect data write.
Japanese Open Laid Patent Application No. 2000-276883 discloses a flash memory for reducing write access time. The disclosed flash memory includes a control circuit which controls the data write sequence in response to commands selectively requesting programming the whole addressed block or programming part of the addressed block.
Japanese Open Laid Patent Application No. 2000-285092 discloses a flash memory in which erasing and programming are independently executed in response to separate commands. Erasing an addressed block is executed in response to an erase command, while programming an addressed block is executed in response to a program command.
Japanese Open Laid Patent Application No. Showa 61-122770 discloses a memory access controller for achieving fast serial data transfer between a memory device and peripheral devices. This memory access controller includes an initial memory address register for providing an initial memory address, and an address counter which generates a memory address by incrementing the memory address from the initial memory address. The address counter basically increments the memory address by one, and increases the memory address by two or more when the increment of the memory address reaches a predetermined value.
Although pre-verification is inevitable for flash memories, the pre-verification undesirably increases write access time of the flash memories. For example, the flash memory disclosed in FIG. 1 requires 32 data verification cycles to complete the pre-verification, because the page buffer 4 includes 32 pages and the comparator circuit 83 compares the data from the page buffer 4 and the memory cell array 8 in units of pages. Executing repeated data verifications undesirably increases the write access time.
In fact, the pre-verification is not necessary with respect to all the pages of the page buffer 4. Data write usually involves updating some, not all, of the pages within the page buffer 4. The pre-verification is necessary for only updated pages of the page buffer 4.